Field of the Invention
The invention relates to a dynamic random access memory (DRAM) controller and DRAM control method, and more particularly, to a method for speeding up memory clock frequency change flow within a computing system, and an apparatus thereof.
Description of the Related Art
Dynamic random access memory (DRAM) is a type of volatile memory that stores each data bit in an individual capacitor. DRAM has a variety of forms such as synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, DDR2 SDRAM, and DDR3 SDRAM, which have different respective densities or operating speeds.
A memory controller, such as a DRAM controller, is a circuit that manages the flow of data to and from a memory such as DRAM. The memory controller controls reading and writing by selecting row and column data addresses of the memory.
As modern computing systems are required to provide more computing capability, integrated circuit (IC) chips or system on chip (SoC) within these computing systems are operating at increasingly faster clock speeds. At the same time, these IC chips consume more power due to faster clock speeds. However, in many computing environments such as a mobile computing system, it is desirable to reduce power consumption. One common technique to save power is to dynamically manage system power consumption through clock-frequency scaling. For example, the clock frequency for an IC may be reduced during periods of operation when the workload is light, thereby reducing power consumption. Note that, when the workload increases again, the clock frequency can be restored to its previous level.
A memory subsystem within a computer system consumes a significant amount of power. Hence, providing power savings in a memory subsystem through dynamic clock-frequency scaling is not uncommon. Changing the clock frequency of a DRAM typically involves: pausing or discarding all outstanding memory subsystem operations; changing the DRAM clock frequency to a new value; and resuming or repeating the memory operations. Unfortunately, suspending memory operations for a long period of time during clock frequency changes is not desirable for many applications, in particular during real-time applications such as audio and video playback. In order not to suffer system performance degradation, fastening the clock frequency change flow of a DRAM subsystem as quickly as possible while satisfying relevant DRAM operation timing constraints to avoid a system malfunction is needed.
Hence, there is a need for a clock frequency changing technique to speed up the DRAM clock frequency change flow efficiently.